1. Field of the Invention
The invention relates to MOS circuits, and in particular to MOS circuits for producing a fixed time delay.
2. Description of the Prior Art
Fixed time delays are difficult to obtain in MOS circuits due to variations in process parameters. It is difficult to implement precision fixed capacitors and resistors in a MOS integrated circuit, thus making RC constants difficult to attain. Prior art schemes include: (1) stage delays using strings of inverters; (2) RC delays using FETs as resistors and capacitors or using N+ or poly as a distributed RC. These prior art techniques provide delays that may track logic delays in the same circuit. However, due to process variations (e.g. thresholds, mobility, N+ and poly resistivities or thickness, oxide and junction capacitances, etc.), these circuits have variations in delays of over 8 to 1. (This factor is estimated based upon computer simulations of process extremes). Sometimes a delay is required that must fit a "window" smaller than the 8:1 variation. For instance, a delay may be required that is greater than 20 ns and less than 80 ns, a range of only 4:1. Prior to the present invention it has not been possible to achieve such an accurate time delay in an MOS integrated circuit.